Semiconductor memory devices constitute an essential part of computer systems due to the relatively high access speeds obtainable and the generally low cost of such devices. One type of semiconductor memory device that is particularly advantageous is the dynamic random access memory device (DRAM), which utilizes a single transistor and capacitor per memory cell in a memory array structure. The simplicity of this design permits the fabrication of memory devices of relatively high density while providing the lowest cost per bit of any memory device currently available.
Memory devices, such as DRAM, are most commonly identified according their data storage handling capability, generally referred to as the capacity of the device. For example, a 128 megabit DRAM device contains approximately 134 million memory cells, each capable of storing a discrete logic state, or bit, in an array having a predetermined number of rows and columns. In practical devices, information is stored in address locations that include more than a single bit, so that the 128 Mb DRAM may be configured, for example, as a 32 Mb device having 4 bits per address, which is commonly referred to as a 32 Mb×4 device. Alternatively, other configurations are possible, since the 128 Mb DRAM may also be configured with 8 or 16 bits per address to form a 16 Mb×8 or an 8 Mb×16 devices, respectively. Other configurations are also well known, and include DRAM devices having memory arrays arranged in banks of predetermined size.
In order to specify an address location for the reading or writing of data to the DRAM, address lines are provided so that the device may accept address inputs. The number of address lines required depends in general on the particular configuration selected for the device. Referring once again to the exemplary 128 megabit DRAM device, if the device is configured as a 32 Mb×4 device, 25 address lines are required. Correspondingly, if the device is configured as a 16 Mb ×8 , or a 8 Mb×16 device, the required number of address lines are 24 and 23, respectively. Thus, the number of address lines changes as the memory configuration changes. In addition, the number of data input/output lines to the device also depends on the selected configuration. For example, for the ×16 configuration, sixteen data input/output lines are required, while the ×8 configuration requires only eight. Still fewer are required for the ×4 configuration.
During the DRAM manufacturing process, address lines and data input/output lines are formed on the die to support all of the desired memory configurations. The device is then configured to correspond to a single memory device by various methods. Most commonly, fuses are formed in the die that may be selectively opened to form the desired address lines and data input/output lines. Alternatively, anti-fuses may be formed in the die that form the desired address lines and data input/output lines when a suitable programming voltage is applied. In either case, the device generally may not be further reconfigured into any other of the possible single memory devices, since the configuration process is irreversible. Consequently, address lines and data input/output lines are often formed on the die that cannot be used in the configured device.
A particular disadvantage associated with the foregoing configuration procedure is encountered during the testing of the device. Typically, a die is subjected to a number of production test procedures in order to verify that the die is fully operational. During one portion of the test procedure, a predetermined test pattern is written to a selected address, and then subsequently read from the same address. If the address location fails to produce the same pattern that was initially written, an error is noted. If the same pattern is detected, the address location is verified as functional, and the test is continued until a defective memory address is detected, or alternatively, the test is completed without detecting any defective addresses. When testing is performed on the die, the testing generally proceeds according to a “wide” test format, wherein the size of each address is large. For example, the 128 megabit DRAM device described earlier may have addresses as large as 16 bits, or 32 bits or even larger addresses during wide testing. Following the completion of the testing, the die is configured into a particular memory device, and is packaged, which generally includes forming connections between various portions of the die and conductors on the package.
Following the packaging procedure, the device is subjected to additional tests that also generally include testing the address locations in the die in the manner described above. Since the device has been configured, however, the ability to test memory addresses by a wide test procedure is no longer possible, since the device has been configured to include addresses of smaller size. Accordingly, a “narrow” test format must be used in post-packaging testing of address locations. Since narrow test procedure must test more address locations that the wide test procedure, more time is required to complete the post-packaging testing using the narrow test.
A packaged memory device may also include more than a single die having suitable interconnections between the individual die that permits the interconnected die to cooperatively form a packaged memory device having a memory capacity that approximates the sum of the memory capacity of the individual die. An example of a multiple die memory device is disclosed in U.S. patent application Ser. No. 10/355,781, filed Jan. 29, 2003 and entitled MULTIPLE CONFIGURATION MULTIPLE CHIP MEMORY DEVICE AND METHOD, which is commonly assigned and is incorporated by reference herein.
A disadvantage present in the foregoing multiple die memory device is that the post-packaging test procedure may reveal that one or more of the individual die has failed. Since the die have been interconnected, packaged and marked, the entire packaged device is generally discarded, even though other die within the package has been verified to be fully operational.
It is therefore desirable to have an apparatus and a method that permits a memory device to be selectively reconfigured, thus permitting the memory device to be tested according to a wide format test procedure after the memory die has been packaged. Further, and with specific reference to multiple die memory devices, it would be desirable to have a multiple die memory device that permits selective reconfiguration so that the operational die within the packaged device may be used.